[SystemSafety] Research topics
Ian Broster
ianb at rapitasystems.com
Mon Jul 15 18:36:05 CEST 2013
Continuing from the comment below, I can note the PROARTIS research
project in this area.
http://www.proartis-project.eu/
The project concerns timing verification, mostly worst case execution time.
The story goes like this:
1. We'd like to use statistics (for the reasons outlined nicely by Tom
Ferrell)
2. If we make the hardware/software have time-randomized behaviour (not
functional!) e.g. random cache replacement, then we can properly
justify/invent/use use statistical methods
3. Now that have the methods - to what extent can they be applied to
systems without novel time-randomized hardware behaviour.
A very interesting and applicable project that is being followed up by a
project called PROXIMA starting later this year.
Ian
On Mon, 15 Jul 2013 15:07:45 +0100, Tom Ferrell <tom at faaconsulting.com>
wrote:
>
> Three from the aviation design assurance area:
>
> 1. Stochastic or empirical validation of individual DO-178B
> objectives
>
> 2. Stochastic or empirical validation of individual DO-254
> objectives
>
> 3. Methods for assuring marginally non-deterministic
> safety-critical embedded >systems
>
>
> The first two are tough due to data access issues but would be
> incredibly useful in >understanding the incremental increases in safety
> margin that accrue from the >application of specific and prescriptive
> design assurance objectives. >Scientifically answered whether we have
> the right objectives has simply not been >accomplished even after
> decades of applying these particular standards. The last >one is a
> realization (IMHO) that the path we are on with ever more prescriptive
> >objectives for demonstrating lock-step determinism in highly complex
> embedded >architectures (e.g., multicore) is likely to be cost
> prohibitive in the near future >and that better value may be obtained by
> abstracting out (in some cases) to a >higher level of determinism. In
> other words, it may be less important to know >exactly what is happening
> at each clock count at the digital level than it is to >know I get a
> bounded response within a defined time window.
>
> From: systemsafety-bounces at techfak.uni-bielefeld.de
> [mailto:systemsafety-bounces at techfak.uni->bielefeld.de] On Behalf Of
> René Senden
> Sent: Monday, July 15, 2013 9:54 AM
> To: systemsafety at techfak.uni-bielefeld.de
> Subject: Re: [SystemSafety] Research topics
>
>
> Contribution from Andy Loebl...
>
>
> From: Loebl, Andy [mailto:loeblas at ornl.gov]Sent: maandag 15 juli 2013
> 14:40
> To: René Senden
> Subject: RE: [SystemSafety] Research topics
>
>
> 1—Waste, Fraud and Abuse in U.S. Public Healthcare claims data.
>
> 2—Physics based Electricity Grid modeling in the U.S. for understanding
> demand-side >system faults causing outages.
>
> 3—extending STAMP to understand U.S. security systems vulnerabilities to
> terrorism
>
>
> From: systemsafety-bounces at techfak.uni-bielefeld.de
> [mailto:systemsafety-bounces at techfak.uni->bielefeld.de] On Behalf Of
> René Senden
> Sent: Sunday, July 14, 2013 6:13 AM
> To: systemsafety at techfak.uni-bielefeld.de
> Subject: [SystemSafety] Research topics
>
>
> Suppose you were to prioritize, say, 3 research topics. Which would you
> select?
--
Ian Broster
Rapita Systems Ltd
Tel: +44 1904 567 747
Mob: +44 7963 469 090
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