[SystemSafety] multi-core validation for aerospace

[paul_e.bennett at topmail.co.uk]

On 14/11/2018 at 11:32 AM, "Tom Ferrell" <tom at faaconsulting.com> wrote:
>
>Concerning this topic in civil aviation:  The current multi-core 
>guidance from both the FAA and EASA cannot be viewed in isolation, 
> Both regulators have additional guidance for dealing with COTS 
>microcontrollers.  While it used to be the case that a 
>microprocessor could be 'accepted' without further compliance 
>demonstration IFF the software test program was conducted on 
>target such that the processor's suitability could be inferred 
>through this test exposure, those days are over for all but the 
>most 'simple' microprocessors.  The additional guidance relates to 
>handling of device errata, levels of change control, service 
>experience in the market, and targeted verification to prove 
>unused capabilities are benign.

Perhaps his is why companies like MicroCore are finding favour in such
environments with their work on developing processor cores in FPGA's
that exercise the logic requirements and gradually paint the processor out
of the design, just leaving the hardware logic behind.


Regards

Paul E. Bennett IEng MIET
Systems Engineer
Lunar Mission One Ambassador
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